Lieze Schindler (リーゼ シンドラー)

Lieze Schindler

所属組織

先端科学高等研究院

職名

特任教員(助教)


学位 【 表示 / 非表示

  • Doctor of Philosophy - ステレンボッシュ大学(南アフリカ共和国)

学内所属歴 【 表示 / 非表示

  • 2022年4月
    -
    現在

    専任   横浜国立大学   先端科学高等研究院   特任教員(助教)  

 

学位論文 【 表示 / 非表示

  • The development and characterisation of a parameterised RSFQ cell library for layout synthesis

    Lieze Schindler

    Stellenbosch University   2021年3月

    学位論文(博士)   単著    [査読有り]

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論文 【 表示 / 非表示

  • Application of Phase-Based Circuit Theory to RSFQ Logic Design

    Lieze Schindler; Coenrad J. Fourie

    IEEE Transactions on Applied Superconductivity   32 ( 3 )   2022年4月  [査読有り]

    DOI

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:IEEE   単著  

    In contrast to transistor-based semiconductor circuits, there is currently no widely accepted formalized circuit theory or design methodology for superconductor rapid single flux quantum (RSFQ) logic circuits. Experienced designers intuitively consider flux loops, nodal phase, and branch currents when making design choices, but the lack of a formalized design process makes it difficult for inexperienced RSFQ circuit designers to construct a functioning logic cell without a reference. This results in new circuit designers, mostly recycling templates from published circuit designs without fully understanding why the circuits function as they do. Inexperienced RSFQ circuit designers often follow an iterative process where cell parameter values are adjusted, and the cell is run through electronic simulation engines until the desired functionality is reached. We propose the development of a formalized circuit design theory for RSFQ logic from first principles using phase-based circuit analysis. The circuit is designed using dc analysis to establish the dc operating point of the circuit. Phase-based analysis and simulation are then used to verify the dynamic circuit functionality. To demonstrate this method, we discuss examples for well-known RSFQ cells. We analyze the initial operating margins of these designs and discuss design accuracy and efficiency. Methods for current regulation to minimize current leakage between cells are discussed. We also present how this design methodology can be used to design new circuits such as an RSFQ XNOR cell. We investigate how an inverting (NOT) cell can be combined with other logic cells to minimize cell latency.

    その他リンク: https://ieeexplore.ieee.org/document/9681154

  • The ColdFlux RSFQ Cell Library for MIT-LL SFQ5ee Fabrication Process

    Lieze Schindler; Johannes A. Delport; Coenrad J. Fourie

    IEEE Transactions on Applied Superconductivity   32 ( 2 )   2022年3月  [査読有り]

    DOI

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:IEEE   共著  

    The ColdFlux project, within the IARPA SuperTools program, aims to develop an open-source EDA tool suite for superconductor circuits, with focus on Rapid single flux quantum (RSFQ) and Adiabatic quantum-flux-parametron (AQFP) logic. The functionality of the ColdFlux tool suite is validated through the development of ready-to-use cell libraries. The process of establishing the open-source ColdFlux RSFQ cell library is documented, along with the set of EDA tools developed within the project required for each step. This includes the initial cell design using phase-based equations, circuit simulation, operating margin analysis, and cell parameter optimization. The row-based layout architecture for the RSFQ cell library is also presented. Several of the designed RSFQ cells are placed within test circuits and fabricated through the MIT-LL SFQ5ee fabrication process. We present the measured results for these test circuits and discuss design efficiency, potential improvements, and future work.

    その他リンク: https://ieeexplore.ieee.org/document/9653858

  • Design and Characterization of Track Routing Architecture for RSFQ and AQFP Circuits in a Multilayer Process

    Coenrad Johann Fourie; Christopher Lawrence Ayala; Lieze Schindler; Tomoyuki Tanaka; Nobuyuki Yoshi … 全著者表示

    IEEE Transactions on Applied Superconductivity   30 ( 6 )   2020年9月  [査読有り]

    DOI

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    記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:IEEE   共著  

    Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

    その他リンク: https://ieeexplore.ieee.org/document/9072514

  • Impedance Matching of Passive Transmission Line Receivers to Improve Reflections Between RSFQ Logic Cells

    Lieze Schindler; Paul le Roux; Coenrad J. Fourie

    IEEE Transactions on Applied Superconductivity   30 ( 2 )   2020年3月  [査読有り]

    DOI

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    担当区分:筆頭著者, 責任著者   記述言語:英語   掲載種別:研究論文(学術雑誌)   出版者・発行元:IEEE   単著  

    Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

    その他リンク: https://ieeexplore.ieee.org/document/8951137

  • Standard Cell Layout Synthesis for Row-Based Placement and Routing of RSFQ and AQFP Logic Families

    Lieze Schindler, Ruben van Staden, Coenrad J. Fourie, Christopher L. Ayala, Johannes A. Coetzee, To … 全著者表示

    2019 IEEE International Superconductive Electronics Conference (ISEC)   2019年

    DOI

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    担当区分:筆頭著者   記述言語:英語   掲載種別:研究論文(国際会議プロシーディングス)   出版者・発行元:IEEE   共著  

    In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.

    その他リンク: https://ieeexplore.ieee.org/document/8990962

研究発表 【 表示 / 非表示

  • Cell design methodology and circuit theory of RSFQ logic

    Lieze Schindler

    European Conference on Applied Superconductivity (EUCAS)  2019年9月 

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    開催年月日: 2019年9月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Glasgow, UK  

  • Standard cell layout synthesis for row-based placement and routing of RSFQ and AQFP logic families

    Lieze Schindler

    International Superconductive Electronics Conference (ISEC)  2019年8月  IEEE-CSC

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    開催年月日: 2019年7月 - 2019年8月

    記述言語:英語   会議種別:口頭発表(一般)  

    開催地:Riverside, CA, USA  

  • Formalising cell design methodology and circuit theory of RSFQ

    Lieze Schindler

    International Symposium on Superconductivity 

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    開催年月日: 2020年12月

    記述言語:英語   会議種別:口頭発表(一般)  

  • Optimization of passive transmission lines to minimize reflections between RSFQ logic cells

    Lieze Schindler

    Applied Superconductivity Conference (ASC) 

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    開催年月日: 2018年10月 - 2018年11月

    記述言語:英語   会議種別:ポスター発表  

    開催地:Seattle, WA, USA