INOUE Fumihiro

Affiliation

Faculty of Engineering, Division of Systems Research

Job Title

Associate Professor

Research Fields, Keywords

Unit processes for 3D integration, advanced packaging

Web Site

https://inoue.ynu.ac.jp/en/

Related SDGs




ORCID  https://orcid.org/0000-0003-2292-846X

写真a

Degree 【 display / non-display

  • Doctor of Engineering - Kansai University

Campus Career 【 display / non-display

  • 2021.4
     
     

    Duty   Yokohama National UniversityFaculty of Engineering   Division of Systems Research   Associate Professor  

  • 2024.4
     
     

    Concurrently   Yokohama National UniversityInstitute for Multidisciplinary Sciences   Associate Professor  

  • 2022.10
     
     

    Concurrently   Yokohama National UniversityInstitute of Advanced Sciences   Associate Professor  

External Career 【 display / non-display

  • 2011.3
    -
    2014.10

    imec  

  • 2013.4
    -
    2014.10

    Tohoku University   Special researcher of the Japan Society for the Promotion of Science  

  • 2014.10
    -
    2021.3

    imec   Researcher  

 

Books 【 display / non-display

  • Exploring Bond Strength for Advanced Chiplet with Hybrid Bonding

    Fuse, J.; Iwata, T.; Yoshihara, Y.; Sano, M.; Inoue, F.( Role: Joint author ,  vol28, (1) 39-45)

    Chip Scale Review 

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    Language:English Book type:Scholarly book

Papers 【 display / non-display

  • 横浜国立大学・井上先生の取り組み

    井上 史大, 今井 正芳

    精密工学会誌   91 ( 7 )   731 - 734   2025.7

    DOI CiNii Research

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    Language:Japanese   Publishing type:Research paper (scientific journal)   Publisher:公益社団法人 精密工学会   Joint Work  

  • Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration

    Kitagawa Hayato, Sato Ryosuke, Ebiko Sodai, Nagata Atsushi, Ahn Chiwoo, Kim Yeounsoo, Kang Jiho, Ue … Show more authors

    ACS Omega   10 ( 25 )   27575 - 27584   2025.6

    CiNii Research

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:American Chemical Society   Joint Work  

    Wafer bonding is a step in processing of state-of-theartintegration architectures in CMOS devices. Sufficiently high bonding strength and low distortion with high alignment accuracy are essential to realize these device structures. A challenge in realizing advanced architectures is reducing the thermal history associated with the bonding process. Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface mechanisms during low temperature annealing have been insufficient. In this study, plasma-activated bonding was carried out using SiCN, which is a major bonding dielectric material. The bonding strength and water remaining at the interface were subsequently evaluated. We found that a SiCN film achieved greater bonding strength after post bond annealing at a low temperature of 250 °C and completely consumed the interfacial water. Analyses of the surface and interface revealed the carbon bonding leads to great bonding interface by low-temperature annealing.

  • Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration

    Kitagawa, H; Sato, R; Ebiko, S; Nagata, A; Ahn, C; Kim, Y; Kang, J; Uedono, A; Inoue, F

    ACS OMEGA   10 ( 25 )   27575 - 27584   2025.6

    DOI Web of Science PubMed

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    Language:English   Publishing type:Research paper (scientific journal)   Joint Work  

  • Direct Physical Vapor Deposition of Liquid Metal on Treated Metal Surface

    Matsuda, R; Isano, Y; Onishi, K; Ota, H; Inoue, F

    ACS APPLIED ELECTRONIC MATERIALS   7 ( 9 )   3656 - 3666   2025.4  [Reviewed]

    DOI Web of Science

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    Language:English   Publishing type:Research paper (scientific journal)   Joint Work  

  • Direct Physical Vapor Deposition of Liquid Metal on Treated Metal Surface

    Matsuda Ryosuke, Isano Yuji, Onishi Koki, Ota Hiroki, Inoue Fumihiro

    ACS Applied Electronic Materials   7   A - K   2025.4

    CiNii Research

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    Language:English   Publishing type:Research paper (scientific journal)   Publisher:American Chemical Society   Joint Work  

    Liquid metal has garnered significant interest as a potential stretchable wiring material for next-generation stretchable electronics. The operation of substrates within these electronics necessitates adherence to three primary criteria for the wiring of electronic substrates to facilitate the integration of stretchable circuits in society. First, the wiring’s top surface must remain exposed to allow for the straightforward attachment of electronic components following the wiring fabrication. Second, the design of the wiring pattern should not be subject to significant constraints. Third, the substrate’s top surface needs to be clean and devoid of excess conductive material to mitigate the risk of unintended short-circuits. Previous studies have not introduced a liquid metal patterning method that meets all of these criteria. Physical vapor deposition (PVD) is commonly employed for depositing hard metals on nonstretchable substrates such as silicon and glass. However, when subjected to direct PVD, liquid metal forms independent nanoparticles, losing conductivity due to its exceptionally high surface tension and the presence of surface oxide films. Consequently, the direct deposition of liquid metals without subsequent physical stimulation, such as the application of pressure, has been deemed challenging. In our study, we enhanced the substrate surface’s wettability by treating it with copper chloride, thereby facilitating the direct deposition of liquid metals onto the substrate surface. The oxide film on the liquid metal’s surface is disrupted upon contact with the copper chloride-treated substrate, enabling the nanoparticles to coalesce and establish electrical connectivity, thereby preserving conductivity even when stretched. The resultant stretchable wiring exhibited a fine line width of approximately 50 μm and a thin film thickness of approximately 1 μm, ensuring a robust bond with the substrate surface. Consequently, this wiring technique supports diverse patterning designs when combined with processing methods such as photolithography.

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Review Papers 【 display / non-display

Awards 【 display / non-display

  • 令和6年度科学技術分野の文部科学大臣表彰【若手科学者賞】

    2024.4   文部科学省  

    Individual or group name of awards:井上史大

  • 第37回 独創性を拓く 先端技術大賞 経済産業大臣賞

    2024.7   産経新聞社   ハイブリッド接合の開発と省電力チップレット集積技術への適用

    Individual or group name of awards:井上史大

  • 第30回半導体・オブ・ザ・イヤー2024 半導体製造装置部門 優秀賞

    2024.6   電子デバイス産業新聞(発行:株式会社産業タイムズ社)   「新たなチップ集積手法によるDie-to-Wafer ハイブリッド接合技術の開発

    Individual or group name of awards:井上史大

  • Best Student Award

    2023.11   ICPT2023   Optimization of Pre-Bonding Surface for Cu/SiCNHybrid Bonding

    Individual or group name of awards:Kohei Nakayama

  • MES2022 ベストペーパー賞

    2023.9   エレクトロニクス実装学会   ハイブリッド接合に向けた化学機械研磨中の金属腐食挙動の解析

    Individual or group name of awards:岩田 知也、中山 航平、布施 淳也、蛯子 颯大、大西 洸輝、北川 颯人、井上 史大(横浜国立大学)

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Preferred joint research theme 【 display / non-display

  • Semiconductor manufacturing processes

  • Hybrid bonding

  • CMP

  • Electrochemical deposition

  • Direct bonding

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Charge of on-campus class subject 【 display / non-display

  • 2025   Advanced Semiconductor Manufacturing

    Interfaculty Graduate School of Innovative and Practical Studies

  • 2025   Studio of Process Integration B

    Graduate school of Engineering Science

  • 2025   Studio of Process Integration A

    Graduate school of Engineering Science

  • 2025   Manufacturing of Processing Systems B

    Graduate school of Engineering Science

  • 2025   Manufacturing of Processing Systems A

    Graduate school of Engineering Science

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Media Coverage 【 display / non-display

  • チップレット集積の課題は山積み、うかうかできない日本企業

    日経BP  日経XTECH  2024.2

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    Author:Other 

  • 「後工程から日本の半導体を盛り返したい」…横浜国立大准教授が3D集積技術に挑む

    日刊工業新聞  日刊工業新聞 ニュースイッチ  2024.2

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    Author:Other