Affiliation |
Faculty of Engineering, Division of Systems Research |
Job Title |
Associate Professor |
Research Fields, Keywords |
Unit processes for 3D integration, advanced packaging |
Web Site |
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Related SDGs |
INOUE Fumihiro
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Degree 【 display / non-display 】
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Doctor of Engineering - Kansai University
Campus Career 【 display / non-display 】
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2021.4
Duty Yokohama National UniversityFaculty of Engineering Division of Systems Research Associate Professor
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2024.4
Concurrently Yokohama National UniversityInstitute for Multidisciplinary Sciences Associate Professor
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2022.10
Concurrently Yokohama National UniversityInstitute of Advanced Sciences Associate Professor
External Career 【 display / non-display 】
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2011.3-2014.10
imec
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2013.4-2014.10
Tohoku University Special researcher of the Japan Society for the Promotion of Science
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2014.10-2021.3
imec Researcher
Books 【 display / non-display 】
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Exploring Bond Strength for Advanced Chiplet with Hybrid Bonding
Fuse, J.; Iwata, T.; Yoshihara, Y.; Sano, M.; Inoue, F.( Role: Joint author , vol28, (1) 39-45)
Chip Scale Review
Language:English Book type:Scholarly book
Papers 【 display / non-display 】
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横浜国立大学・井上先生の取り組み
井上 史大, 今井 正芳
精密工学会誌 91 ( 7 ) 731 - 734 2025.7
Language:Japanese Publishing type:Research paper (scientific journal) Publisher:公益社団法人 精密工学会 Joint Work
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Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
Kitagawa Hayato, Sato Ryosuke, Ebiko Sodai, Nagata Atsushi, Ahn Chiwoo, Kim Yeounsoo, Kang Jiho, Ue … Show more authors
Kitagawa Hayato, Sato Ryosuke, Ebiko Sodai, Nagata Atsushi, Ahn Chiwoo, Kim Yeounsoo, Kang Jiho, Uedono Akira, Inoue Fumihiro Hide authors
ACS Omega 10 ( 25 ) 27575 - 27584 2025.6
Language:English Publishing type:Research paper (scientific journal) Publisher:American Chemical Society Joint Work
Wafer bonding is a step in processing of state-of-theartintegration architectures in CMOS devices. Sufficiently high bonding strength and low distortion with high alignment accuracy are essential to realize these device structures. A challenge in realizing advanced architectures is reducing the thermal history associated with the bonding process. Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface mechanisms during low temperature annealing have been insufficient. In this study, plasma-activated bonding was carried out using SiCN, which is a major bonding dielectric material. The bonding strength and water remaining at the interface were subsequently evaluated. We found that a SiCN film achieved greater bonding strength after post bond annealing at a low temperature of 250 °C and completely consumed the interfacial water. Analyses of the surface and interface revealed the carbon bonding leads to great bonding interface by low-temperature annealing.
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Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration
Kitagawa, H; Sato, R; Ebiko, S; Nagata, A; Ahn, C; Kim, Y; Kang, J; Uedono, A; Inoue, F
ACS OMEGA 10 ( 25 ) 27575 - 27584 2025.6
Language:English Publishing type:Research paper (scientific journal) Joint Work
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Direct Physical Vapor Deposition of Liquid Metal on Treated Metal Surface
Matsuda, R; Isano, Y; Onishi, K; Ota, H; Inoue, F
ACS APPLIED ELECTRONIC MATERIALS 7 ( 9 ) 3656 - 3666 2025.4 [Reviewed]
Language:English Publishing type:Research paper (scientific journal) Joint Work
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Direct Physical Vapor Deposition of Liquid Metal on Treated Metal Surface
Matsuda Ryosuke, Isano Yuji, Onishi Koki, Ota Hiroki, Inoue Fumihiro
ACS Applied Electronic Materials 7 A - K 2025.4
Language:English Publishing type:Research paper (scientific journal) Publisher:American Chemical Society Joint Work
Liquid metal has garnered significant interest as a potential stretchable wiring material for next-generation stretchable electronics. The operation of substrates within these electronics necessitates adherence to three primary criteria for the wiring of electronic substrates to facilitate the integration of stretchable circuits in society. First, the wiring’s top surface must remain exposed to allow for the straightforward attachment of electronic components following the wiring fabrication. Second, the design of the wiring pattern should not be subject to significant constraints. Third, the substrate’s top surface needs to be clean and devoid of excess conductive material to mitigate the risk of unintended short-circuits. Previous studies have not introduced a liquid metal patterning method that meets all of these criteria. Physical vapor deposition (PVD) is commonly employed for depositing hard metals on nonstretchable substrates such as silicon and glass. However, when subjected to direct PVD, liquid metal forms independent nanoparticles, losing conductivity due to its exceptionally high surface tension and the presence of surface oxide films. Consequently, the direct deposition of liquid metals without subsequent physical stimulation, such as the application of pressure, has been deemed challenging. In our study, we enhanced the substrate surface’s wettability by treating it with copper chloride, thereby facilitating the direct deposition of liquid metals onto the substrate surface. The oxide film on the liquid metal’s surface is disrupted upon contact with the copper chloride-treated substrate, enabling the nanoparticles to coalesce and establish electrical connectivity, thereby preserving conductivity even when stretched. The resultant stretchable wiring exhibited a fine line width of approximately 50 μm and a thin film thickness of approximately 1 μm, ensuring a robust bond with the substrate surface. Consequently, this wiring technique supports diverse patterning designs when combined with processing methods such as photolithography.
Review Papers 【 display / non-display 】
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Inoue, F. and Podpod, A. and Peng, L. and Phommahaxay, A. and Rebibis, K.J. and Uedono, A. and Beyn … Show more authors
Inoue, F. and Podpod, A. and Peng, L. and Phommahaxay, A. and Rebibis, K.J. and Uedono, A. and Beyne, E. Hide authors
Journal of Manufacturing Processes 58 811 - 818 2020 [Reviewed] [Invited]
Language:Japanese Publishing type:Article, review, commentary, editorial, etc. (bulletin of university, research institution) Joint Work
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Film Characterization of Low-Temperature Silicon Carbon Nitride for Direct Bonding Applications
Nagano, F. and Iacovo, S. and Phommahaxay, A. and Inoue, F. and Sleeckx, E. and Beyer, G. and Beyne … Show more authors
Nagano, F. and Iacovo, S. and Phommahaxay, A. and Inoue, F. and Sleeckx, E. and Beyer, G. and Beyne, E. and De. Gendt, S. Hide authors
ECS Journal of Solid State Science and Technology 9 ( 12 ) 2020 [Reviewed] [Invited]
Language:Japanese Publishing type:Article, review, commentary, editorial, etc. (bulletin of university, research institution) Joint Work
Awards 【 display / non-display 】
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令和6年度科学技術分野の文部科学大臣表彰【若手科学者賞】
2024.4 文部科学省
Individual or group name of awards:井上史大
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2024.7 産経新聞社 ハイブリッド接合の開発と省電力チップレット集積技術への適用
Individual or group name of awards:井上史大
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第30回半導体・オブ・ザ・イヤー2024 半導体製造装置部門 優秀賞
2024.6 電子デバイス産業新聞(発行:株式会社産業タイムズ社) 「新たなチップ集積手法によるDie-to-Wafer ハイブリッド接合技術の開発
Individual or group name of awards:井上史大
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Best Student Award
2023.11 ICPT2023 Optimization of Pre-Bonding Surface for Cu/SiCNHybrid Bonding
Individual or group name of awards:Kohei Nakayama
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MES2022 ベストペーパー賞
2023.9 エレクトロニクス実装学会 ハイブリッド接合に向けた化学機械研磨中の金属腐食挙動の解析
Individual or group name of awards:岩田 知也、中山 航平、布施 淳也、蛯子 颯大、大西 洸輝、北川 颯人、井上 史大(横浜国立大学)
Preferred joint research theme 【 display / non-display 】
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Semiconductor manufacturing processes
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Hybrid bonding
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CMP
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Electrochemical deposition
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Direct bonding
Charge of on-campus class subject 【 display / non-display 】
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2025 Advanced Semiconductor Manufacturing
Interfaculty Graduate School of Innovative and Practical Studies
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2025 Studio of Process Integration B
Graduate school of Engineering Science
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2025 Studio of Process Integration A
Graduate school of Engineering Science
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2025 Manufacturing of Processing Systems B
Graduate school of Engineering Science
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2025 Manufacturing of Processing Systems A
Graduate school of Engineering Science
Media Coverage 【 display / non-display 】
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チップレット集積の課題は山積み、うかうかできない日本企業
日経BP 日経XTECH 2024.2
Author:Other
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「後工程から日本の半導体を盛り返したい」…横浜国立大准教授が3D集積技術に挑む
日刊工業新聞 日刊工業新聞 ニュースイッチ 2024.2
Author:Other